STATS ChipPAC
(SGX: S24)

STATS ChipPAC Pte. Ltd., formerly STATS ChipPAC Ltd., is a provider of semiconductor packaging and test services. The Company's solutions are used in applications, including communications, digital consumer and computing. Its technology portfolio includes leadframe and laminate packages, fan-out and fan-in wafer level technology (FIWLP), flip chip interconnect and system-in-package (SiP). The Company's manufacturing facilities are located in Singapore, South Korea and China. The Company markets its services through its direct sales force in the United States, South Korea, China, Singapore, Taiwan and Switzerland. The Company's services include post wafer fab process, and back-end assembly and test. The Company offers a platform of wafer level technologies for devices, which include FIWLP, including embedded Wafer Level Ball Grid Array, and Fan-out Wafer Level Packaging (FOWLP), including Wafer Level Chip Scale Packages and encapsulated Wafer Level Chip Scale Packages.
公众假期 <span class="translation_missing" title="translation missing: zh.calendar.SG">Sg</span> - GOOD FRIDAY

3.800 s

-0.120 (-3.06%)
价格区间 3.760 - 3.920   (4.26%)
开盘 3.870
昨收 3.920
3.800
买盘 ('000) 47.1
3.810
卖盘 ('000) 76.9
成交量 ('000) 11,587.7
成交额 -
注释 s
数据延迟。最后一次更新03 Apr 2020 04:50.
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关于 STATS ChipPAC

STATS ChipPAC Pte. Ltd., formerly STATS ChipPAC Ltd., is a provider of semiconductor packaging and test services. The Company's solutions are used in applications, including communications, digital consumer and computing. Its technology portfolio includes leadframe and laminate packages, fan-out and fan-in wafer level technology (FIWLP), flip chip interconnect and system-in-package (SiP). The Company's manufacturing facilities are located in Singapore, South Korea and China. The Company markets its services through its direct sales force in the United States, South Korea, China, Singapore, Taiwan and Switzerland. The Company's services include post wafer fab process, and back-end assembly and test. The Company offers a platform of wafer level technologies for devices, which include FIWLP, including embedded Wafer Level Ball Grid Array, and Fan-out Wafer Level Packaging (FOWLP), including Wafer Level Chip Scale Packages and encapsulated Wafer Level Chip Scale Packages.

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